This invention relates to a PLL (Phase-locked loop) circuit and a method of controlling the same, and in particular, to a PLL circuit which is capable of automatically restoring to a normal state when an oscillation operation is halted on the condition that an oscillation state of a voltage oscillation circuit (VCO) is monitored.
Recently, excessively fine resolution is given for a clock step operation to restore a data signal from a receiving signal in a communication system. To this end, a PLL (Phase-locked loop) circuit, which produces multi-phase clocks, has been required. When the phase number (2, 4, 8, 16, . . . ) of the multi-phase clocks is equal to the Nth power of 2, a circuit for realizing the clock step operation does not require a redundant circuit. Consequently, the circuit can readily and simply be designed.
In this event, eight phase clocks are generally designed among the phase clocks of the Nth power of 2 in the system.
Hereinafter, description will be made about conventional references with respect to the multi-phase clocks.
(1) First conventional reference (Japanese Unexamined Patent Publication (JP-A) No. Hei. 4-20016):
The first conventional reference discloses a clock generator which has a ring oscillator including odd stages of delay circuits and which directly and separately produces output signals of a plurality of the delay circuits as clock signals of multi-phase.
Although this system is generally used, the system can not produce phase clocks of the Nth power of 2.
(2) Second conventional reference (Japanese Unexamined Patent Publication (JP-A) No. Sho. 58-59653):
The second conventional reference discloses a clock generator which has four phase detectors for detecting phase modulation signals of eight phase and which produce clock signals of eight phases by giving output signals of a voltage control oscillator for producing a single phase clock into the phase detector.
This system can produce the phase clocks (eight phase clocks) of Nth power of 2. However, operation speed of the detector is restricted. In consequence, the system can not produce high-speed clocks. Further, it is difficult in design to unify delay times of the four detectors.
(3) Third conventional reference (Japanese Unexamined Patent Publication (JP-A) No. Hei. 8-340241):
The third reference discloses an oscillator of multi-phase to which buffers are connected in series with a plurality of stages. With this structure, an output signal of the final stage is reversed, and is fed back into the first stage of the buffer. Herein, the each of the buffers is composed of two inverters.
In this system, delay time between output decision of the first stage and output decision of the final stage inevitably becomes large in comparison with times necessary to the other portions.
To solve these problems, it is necessary that the ring oscillator of the voltage control oscillator is structured by even devices. To this end, it has been tried to constitute the ring oscillator by using a delay circuit as a differential circuit and by connecting even delay circuits.
However, the following problems occur when the ring oscillator is structured by the even stages.
Namely, in case that the ring oscillator of the even stages is used, the oscillation operation may be halted by an affect of noise when a power supply is introduced.
In the ring oscillator of the even stages illustrated in FIG. 1, even differential amplifiers 81 through 84 are connected in series, and an input of first stage and an output of final stage are connected in a ring form. With such a structure, when the ring oscillator is normally oscillated, all outputs of the differential amplifier are put into unbalanced states. For example, when an output 803 is put into a high level, an output 804 is put into a low level.
In this circuit, when both inputs 801 and 802 of a differential amplifier 81 are put into high levels, outputs 803 and 804 of the differential amplifier 81 are put into low levels, outputs 805 and 806 of a differential amplifier 82 are put into high levels, outputs 807 and 808 of a differential amplifier 83 are put into low levels, and an output of a differential amplifier is put in to high level so as to be given to a first stage.
However, the same high levels are given to outputs 801 and 802 of the differential amplifier 81. Consequently, a normal oscillation state does not appear, and as a result, the oscillation operation inevitably halts.
Recently, the number of detachable devices is increased. Consequently, the number of device having no reset signal (power-on reset signal) when the power supply is introduced is also increased. Herein, it is to be noted that the conventional device has the reset signal.
In consequence, the device can not make an initial value of the PLL circuit. As a result, it is uncertain whether or not the voltage control oscillator accurately oscillates. To solve this problem, a technique, in which the system monitors the output of the PLL circuit and the system is automatically restored to the normal state when the oscillation operation is halted, has been researched.
For example, description has been made about a technique, in which a system monitors an oscillation of a voltage control oscillator in a PLL circuit and the system is automatically restored to the normal oscillation state when the oscillation is halted in Japanese Unexamined Patent Publication (JP-A) No. Hei. 7-74625.
A circuit illustrated in FIG. 2 includes a phase comparing circuit 91, a voltage generating circuit 92, a voltage control oscillator 93, and a self-restoring control circuit 94.
With such a structure, the phase comparing circuit 91 compares a referential signal 901 with an oscillation signal 904 and produces a phase difference detecting signal 902. The voltage generating circuit 92 converts the phase difference detecting signal 902 into a voltage 903. The voltage control oscillator 93 produces a frequency signal proportional to the voltage 903. The self-restoring control circuit 94 monitors the referential signal 901 and the oscillation signal 904, and supplies a self-restoring signal 905 into the phase comparing circuit 91.
In this case, the phase comparing circuit 91 gives the phase difference detecting signal 902 into the voltage generating circuit 92 on the basis of the self-restoring signal 905 given from the self-restoring control circuit 94 at a constant duration after the voltage control oscillator 93 halts. Thereby, the system is self-restored to the normal oscillation state.
However, this conventional technique has the following problems.
First, the voltage control oscillator having even stages of ring oscillator may halt the oscillation even when the voltage from the voltage generating circuit is normal. However, the system can not be automatically restored from this state.
This reason is explained as follows.
The voltage control oscillator having odd stages of ring oscillator inevitably and normally oscillates when the voltage from the voltage generating circuit is normal. The oscillation halts only when the voltage approaches a ground line GND level or a power supply line VDD level. When the oscillation halts, the self-restoring signal is given to the voltage generating circuit, and an output voltage of the voltage generating circuit is put into a normal value. Thus, the self-restoring control is carried out.
However, in this method, when the oscillation of the even stages of ring oscillator halts on the condition that the voltage from the voltage generating circuit is normal, the oscillation can not be restored.
Second, when the PLL circuit halts, it is possible to automatically restore in case that an output level is fixed to a low level. However, it is impossible to automatically restore in case that the output level is fixed to a high level. This is because the self-restoring control is carried out by detecting a timing at which the output level is fixed to the low level as the oscillation halting state.
Further, oscillation frequency is variable proportional to a control voltage from the voltage generating circuit in the ring oscillator. However, when the control voltage approaches the power supply line VDD level or the ground line GND level, the ring oscillator does not become the normal oscillation state, and the oscillation inevitably halts.
In a differential amplifier illustrated in FIG. 3, a drain of a transistor 705 is connected to a drain of a transistor 752. Further, drains of the transistors 751 and 753 are connected to each other. Sources of transistors 750 and 751 are coupled to a power supply line VDD. Sources of transistors 752 and 753 are connected to a drain of a transistor 754. A source of a transistor 754 is coupled to a ground line GND of a transistor 754.
Further, a gate of a transistor 750 is connected to a gate of a transistor 751 to form control input terminal 701 from an external circuit. A gate of a transistor 754 serves as an control input 704 from an external circuit.
Each of gates 702 and 703 of transistors 752 and 753 serves as an input terminal while each of drains 706 and 705 of transistors 752 and 753 serves as an output terminal.
When a high level is given to the input terminal 702 and a low level is given to the input terminal 703, the transistor 752 is put into an ON state, the output 706 is put into the low level, the transistor 753 is put into an OFF state, and the output 705 is put into the high level.
The voltage 903 from the voltage generating circuit 92 is applied to the control inputs 701 and 704 of the transistors 750, 751, and 754, and the delay time of the differential amplifier is variable in dependency upon the voltage. By utilizing this phenomenon, the oscillation frequency of the ring oscillator is changed.
However, when the control inputs 701 and 704 of the transistors 750, 751 and 754 approach the power supply line VDD level or the ground line GND level, each of the transistors 750, 751 and 754 is put into the OFF state, and no current flows.
Consequently, the circuit can not be operable as the differential amplifier, and as a result, the oscillation inevitably halts.
In addition, the related techniques have been disclosed in Japanese Unexamined Patent Publications No. Sho. 55-42443, Sho. 63-185121, Hei. 5-122032, Hei. 8-79068, Hei. 8-307460, and Hei. 9-326692.